1. The Field of the Invention
The present invention involves a selective etching process that utilizes one of an organic masking material and a silicon dioxide layer as etch barriers during the selective etch of a layer of silicon containing material situated on a semiconductor substrate. More particularly, the present invention relates to a process for utilizing an ammonia chemistry etch system for selectively etching an area of a silicon containing material while one of an organic photoresist layer and a BPSG layer are not substantially etched.
2. The Relevant Technology
Modern integrated circuits are manufactured by an elaborate process in which a large number of electronic semiconductor devices are integrally formed on a semiconductor substrate. In the context of this document, the term "semiconductor substrate" is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above.
Conventional semiconductor devices which are formed on a semiconductor substrate include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor substrate. In order to compactly form the semiconductor devices, the semiconductor devices are formed on varying levels of the semiconductor substrate. This requires forming a semiconductor substrate with a topographical design.
Uniformity across a semiconductor device is a concern during the many process steps in the fabrication of a semiconductor device. One of the process steps in the manufacture of these multilayer structures is a chemical mechanical planarization (CMP) process. In the case of a semiconductor wafer subjected to a CMP process, the CMP process may not uniformly planarize a surface on the semiconductor wafer, particularly at along the circular edge of the semiconductor wafer where polishing can be the deepest across the wafer. As a result, an uneven surface is produced. In addition to the problem of uneven surfaces, the CMP may also over polish the semiconductor wafer so as to expose surfaces deep within. Over polishing may reduce yield and can potentially cause electrical shorts.
Commercialized silicon etchants include potassium hydroxide (KOH), tetramethal ammonium hydroxide ((CH.sub.4).sub.4 N--OH), and a mixture of water, hydrofluoric acid (HF), nitric acid (HNO.sub.3), and acetic acid (CH.sub.3 COOH). Such etches, however, do not adequately address the foregoing problems. Additionally, conventional silicon etchants are selective neither to organic photoresist materials nor to silicon dioxide. When potassium (K) is in the etchant, contamination of the semiconductor wafer can result. Consequently, potassium hydroxide (KOH) is not used in some semiconductor laboratories. Also, the carbon chains of a ((CH.sub.4).sub.4 N--OH) etchant render the organic etchant unselective to organic photoresist material.
It would be advantageous to identify a etchant for a silicon containing material, such as CSG polysilicon, HSG polysilicon, polysilicon, monocyrstalline silicon, and amorphous silicon, that is also selective to silicon dioxide and organic photoresist material.